MT46V32M16P-6T 512Mbits DDR333 DDR SDRAM from Micron in TSSOPII-66 Package. Its uses double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock at the I/O pins.

• Bidirectional data strobe (DQS) transmitted/received with data
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Low Standby current (maximum): 2mA full standby
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh and self refresh modes
• 2.5V I/O

• Package: TSSOPII-66
• Operating Temperature: 0° C to +70° C
• Operating Voltage: +2.3V to +2.7V, CL=2.5, t_CK=6ns, 167MHz
• Pb-Free

MT46V32M16P-6T Datasheet